//file name:	top_fpga.v
//author:		ETree
//date:			2017.10.1
//function:		top file of project
//log:

module top_fpga(
	//global signal                           
	input	sys_clk,
	input	rst_n,
	input	key,
	
	//GNET
	inout	MDIO,
	output	MDC,
	output	txer,
	output	txen,
	input 	txclk,
	output	[7:0] tx,
	output	greset,
	output	gtx_clk,
	
	//LED
	output	led
	
);

/*
	Led seems not used by etree.
	Here we set it to be same as key input
*/
assign led = key;


//----------Soft reset----------
reg [15:0] rst_cnt; 
reg rstn;

always @(posedge sys_clk)
begin
	if(!rst_n)
		rst_cnt <= 16'b0;
	else if(rst_cnt>='hfffa)
		rst_cnt <= rst_cnt;
	else
		rst_cnt <= rst_cnt + 1'b1;
end

always @(posedge sys_clk)
begin
	if(!rst_n)
		rstn <= 1'b0;
	if(rst_cnt>='hfff0)
		rstn <= 1'b1;
	else
		rstn <= 0;
end

//key debounce
wire key_valid;

key_jitter key_jitter_inst
(
	.clk(~sys_clk) ,			// input  clk 
	.key_n(key) ,			// input  key_n 
	.key_valid(key_valid) 	// output key_valid 
);				
		
//-----------ETHernet-------------

wire [10:0] frame_index;

assign gtx_clk  = sys_clk;	 
assign greset = 1'b1; 
assign frame_index = 0;

udp udp_inst(
	.rst_n				(rstn),
	.e_clk				(sys_clk),
	.e_txen				(txen),
	.e_txd				(tx),
	.e_txer				(txer),	

//	.key_valid			(1'b1),
	.key_valid			(key_valid),

	.frame_index		(frame_index), 
	
	.tx_total_length	('d60),			//total length of IP package
	.tx_data_length		('d40)          //total length of IP data		
);


endmodule


